1. Field of the Invention
The invention relates to a structure of a trench capacitor and method for manufacturing the same, and more particularly, to a method of manufacturing a trench capacitor in which the STI process is compatible with the logic processes, and in which the capacitor area is effectively increased.
2. Description of the Prior Art
As electrical products tend towards increasing miniaturization, DRAM devices need to have a high integration and density. Trench capacitor DRAM devices are popularly used for high density DRAM that is formed in a deep trench capacitor of the semiconductor substrate to effectively decrease the size of memory unit and efficiently utilize the space of the chip.
Please refer to FIG. 1 to FIG. 4, which are schematic cross-sectional views showing the fabrication of Shallow Trench Isolation (STI) regions between trench capacitors according to a prior art method. As shown in FIG. 1, a semiconductor chip 10 comprises a logic area 16 and a memory array area 14. As indicated, a plurality of trench capacitors 18 has been formed in the semiconductor substrate 12 within the memory array area 14 of the semiconductor chip 10. Typically, each of the trench capacitors 18 is formed by etching a hard mask 20 to form a deep trench opening (not shown) in the silicon substrate 12, and then an electrode of the capacitor (not shown), a poly storage node 24 serving as the other electrode of the capacitor, and a node dielectric layer 22 between the two electrodes are formed in the deep trench opening.
As shown in FIG. 2, a bottom anti-reflection coating (BARC) 26 is deposited on the mask 20, followed by photoresist coating. A conventional lithographic process and subsequent baking process are then carried out to pattern the photoresist coating, thereby forming photo mask 28 defining the trench openings 30 of the memory array 14 and the trench openings 32 of the logic area.
As shown in FIG. 3, using the photo mask 28 as an etching mask, a plasma dry etching is performed to etch the BARC 26, the hard mask 20, the silicon substrate 12, and a portion of the storage node 24 and node dielectric layer 22 through the memory array area trench openings 30 within the memory array area 14, thereby forming isolation trenches 34. The BARC 26, the hard mask 20, and substrate 12 are also etched through the logic area trench openings 32 within the logic area 16, thereby forming isolation trenches 36. Thereafter, the remaining photo mask 28 and the BARC 26 are removed. Finally, as shown in FIG. 4, the isolation trenches 34 and 36 are filled with gap fill dielectric materials 38 and planarized.
However, there are several problems with the above-described prior art STI method of forming trench capacitor DRAM devices. Because trench capacitors 18 are complex, the STI etching process is complex and is not easy to control the STI region 34 formed by etching the BARC 24, the hard mask 20, the silicon substrate 12, the portion of storage node 24, and node dielectric layer 22 through trench openings 30. First, the thick hard mask leads to bad critical dimension (CD) uniformity and large iso/dense CD bias. Secondly, the STI trench recipe is difficult to develop because of the complex structure of the trench capacitor. Thirdly, the above-described prior art STI method for trench capacitor DRAM devices is not compatible with the logic processes.